Embodiments of the present disclosure relate to a semiconductor test device, and more particularly, to a technology for performing a test operation using a high-speed clock signal and data that are internally generated.
As the degree of integration of semiconductor memory devices increases, semiconductor memory devices have been continuously improved upon to increase an operation speed. In order to increase operation speed, synchronous memory devices, which operate by being synchronized with an external clock, have been proposed and developed.
A representative synchronous memory device is a single data rate (SDR) synchronous memory device, which is synchronized with a rising edge of an external clock such that one bit data can be input or output through one data pin during one period of the external clock.
However, it is difficult for a SDR synchronous memory device to perform high-speed operations in a system. In order to solve this problem of the SDR synchronous memory device, a double data rate (DDR) synchronous memory device capable of processing two bits of data during one clock period has been proposed.
Two contiguous bits of data are input and output through respective data input/output (I/O) pins of a DDR synchronous memory device, and the two contiguous bits of data are synchronized with a rising edge and a falling edge of an external clock. Therefore, although a frequency of the external clock does not increase, the DDR synchronous memory device may have a bandwidth that is at least two times larger than that of a SDR synchronous memory device. As a result, the DDR synchronous memory device can operate at a higher speed than the SDR synchronous memory device.
The DDR synchronous memory device is suitable for a multi-bit prefetching scheme capable of simultaneously processing multiple bits (multi-bit) of data. The multi-bit prefetching scheme synchronizes sequential input data with a data strobe signal such that the input data can be arranged in parallel to one another. Thereafter, according to the multi-bit prefetching scheme, the input data arranged in parallel are simultaneously stored upon receiving a write command synchronized with an external clock.
Generally, semiconductor memory devices such as dynamic random access memory (DRAM) devices are designed to support various test operations. In order to decrease production costs and increase productivity of semiconductor memory devices, various tests have been applied to the semiconductor memory devices at a wafer level and a package level.
In testing semiconductor memory devices, it is important to test the reliability of the semiconductor memory devices. In addition, it is important to be able to test many memory cells, for example, in the order of tens of millions of memory cells, at a high speed. Specifically, reduction of a development period of semiconductor memory devices and reduction of a test time consumed in testing manufactured semiconductor memory devices may reduce production costs. As a result, the test time is an important factor for production efficiency and competition between manufacturers.
According to the conventional art, a potential (or latent) defect in an element per bank can be detected only through a test executed at a package level, and the detected defective element can be repaired only at the package level. However, if the detected defective element is repaired at the package level, production time increases and more production costs are consumed compared to other technologies that repair a defective element at a wafer level.
Meanwhile, if a channel for bank selection is allocated during testing at a wafer level, the number of chips (dies) to be tested may be determined depending on the number of channels that are limited. That is, if a probe test device is assigned a small number of channels although a high-speed test should be applied to the probe test device, the number of chips (dies) capable of being simultaneously tested is reduced. As a result, the overall test time unavoidably increases when all chips (dies) on a wafer are tested.
In addition, as an operation speed of semiconductor memory devices rapidly increases, the speeds of a clock and data that a test device is able to provide cannot reach a threshold speed at which semiconductor memory devices operate. Accordingly, a semiconductor test device capable of transmitting input data at a high speed in a test operation is in demand.
As an operation speed of a system including semiconductor devices becomes faster and as technology of semiconductor integrated circuits (ICs) develops, there is a need for semiconductor memory devices that can output/store data at higher speeds. Indeed, semiconductor memory devices capable of storing much more data and reading/writing data at higher speeds are increasingly in demand.
As a result, the design and manufacturing processes of the semiconductor memory devices have become more complicated, and processes for testing the manufactured semiconductor memory devices have also become complicated and difficult to implement. For example, the number of operations to be tested unavoidably increases, and a testing process for each operation is complicated. In other words, as a testing process of semiconductor memory devices having a higher storage capacity and a higher degree of integration becomes more complicated, a more complicated algorithm is used and a longer test time for performing the complicated algorithm are needed.
Accordingly, a conventional testing method for allowing automatic test equipment (ATE) to externally access and test semiconductor memory devices requires a very long test time, resulting in reduction of the test efficiency and productivity of the semiconductor memory devices.